 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ISDN PC Adapter Circuit IPAC PSB/F 2115 Version 1.2 Addendum/Corrections 02.99 to Data Sheet 11.97 1 Back to Back Frames The back to back frame transmission as described in chapter 3.4.1 on pages 177 and 178 is not supported by the chip. 2 Length of FSC Pulse in NT and LT-S Modes In NT and LT-S mode the S/T-interface superframe with 5 ms period can be synchronized to a master device by modulation of the pulse width of FSC. The IPAC samples the FSC input with the second falling edge of DCL in the very first bit of the frame and resets the S/T-interface transmit frame, including multiframe, if the sample bit is zero. The remaining FSC clocks must be of at least two DCL periods duration. Please note, that in a NT application the superframe marker of IEC-Q must be disabled due to different multiframe periods of U- and S-interface. 3 Microprocessor Interface Timing The timing value tRWD is specified as tbd in the Data Sheet 11.97 (page 288). The actual value can be seen from the table below. Parameter R/W hold from CS x DS inactive Symbol tRWD Limit Values min. 5 max. ns Unit Siemens Semiconductor Group (c) Siemens AG 02.99. All Rights Reserved. DS 1 Please note that any information contained in this publication may be subject to change. Siemens reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Please contact our regional offices to receive the latest version of the relevant information to verify, before placing orders, that the information being relied upon is current. Revision History: Previous Version: none Major Changes: PSB/F 2115 4 Pin Definitions and Functions One function of the pins AUX3-5 is not described on page 22. If the PCM interface is disabled (in LT-S and LT-T modes) AUX3-5 can be used as general purpose I/O pins, i.e. same functions as in TE mode. Semiconductor Group 2 02.99 |
Price & Availability of PSB2115-FV12
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |